1. Field of the Invention
The present invention relates to a high speed Exclusive OR logic circuit, and more particularly to a high speed 3-way Exclusive OR logic circuit with essentially a single stage logic delay.
2. Description of the Prior Art
U.S. Pat. No. 2,926,850 to R. K. Richards, issued Mar. 1, 1960 and assigned to the assignee of the present application, shows a 3-way Exclusive OR circuit as a summer portion (23-28, 32-34 of FIG. 2 of the patent) of a binary adder/subtractor. The Exclusive OR circuit disclosed comprises a combination of diode AND circuits, diode OR circuits and inverter circuits. A 3-way OR circuit is provided to produce a "1" output whenever one or more input operands are "1". Three 2-way AND circuits, an OR-Inverter and a 2-way AND circuit are used to inhibit "1" output of the 3-way OR circuit whenever two or more input operands are "1". A 3-way AND circuit is provided to produce "1" output when all of the three input operands are "1". The outputs of the 3-way OR circuit and the 3-way AND circuit are ORed to provide final Exclusive OR function. Because of series combination of several logic elements, the 3-way Exclusive OR circuit disclosed includes three-stage logic delay. In addition, it needs relatively large numbers of logic elements.
U.S. Pat. No. 2,850,647 to H. Fleisher, issued Sept. 2, 1958 and assigned to the assignee of the present application, shows a 2-way Exclusive OR circuit. A block diagram of FIG. 5 of the patent shows that an output from a 2-way OR circuit and an output from a 2-way AND circuit are combined in an Inhibit circuit (AND plus INV) to obtain 2-way Exclusive OR function. Although this patent uses the output of the 2-way AND circuit to inhibit the output of the 2-way OR circuit when both input operands are "1", it does not teach any specific manner to perform 3-way Exclusive OR function with essentially a single stage logic delay.
U.S. Pat. No. 3,649,844 to F. K. Kroos, issued Mar. 14, 1972 and assigned to Siemens AG, shows a 3-way Exclusive OR circuit. It uses four current switches constructed in accordance with two-level current switch tree configuration. Because of this configuration, the 3-way Exclusive OR circuit disclosed requires a level shifter for one of the input operands, and a higher voltage supply than is usually required for one-level current switch circuit.
U.S. Pat. No. 4,041,326 to B. J. Robinson, issued Aug. 9, 1977 and assigned to FCI Corp., shows a 3-way Exclusive OR circuit implemented by current switches. This circuit, however, requires both true and complement input operands for each of the three input operands. This means that one-stage logic delay is additionally included to produce complement forms of input operands. In addition, the circuit disclosed uses a three-level current switch tree which requires higher voltage supply and two levels of logic level shifters.
U.S. Pat. No. 2,927,733 to C. M. Campbell, Jr., issued Mar. 8, 1960 and assigned to Burroughs Corp., shows a 3-way Exclusive OR which comprises a combination of NPN transistor current switches and PNP transistor current switches. Since the PNP transistor current switches are included, the operation speed of the circuit is slow because the PNP transistor circuit is normally two to three times as slow as the NPN circuit. In addition, time-consuming and complicated process is needed to construct the PNP-NPN transistor circuit on a single chip.
IBM Technical Disclosure Bulletin by J. E. Gersbach, entitled "FOUR-WAY EXCLUSIVE-OR", Vol. 11, No. 9, February 1969, pages 1162-1163 shows a 4-way Exclusive OR circuit which uses a two-level current switch tree. In addition, this circuit requires true form of input operands for two operands and complement form of input operands for two other operands.
IBM Technical Disclosure Bulletin by J. E. Gersbach entitled "CASCODE EXCLUSIVE OR", Vol. 19, No. 6, November 1976, pages 2010-2011, shows a 5-way Exclusive OR circuit implemented by a five-level cascode current switch tree which requires a high voltage supply and several level shifters.
IBM Technical Disclosure Bulletin by F. H. Lohrey et al entitled "GATED EXCLUSIVE OR CIRCUIT", Vol. 19, No. 6, November 1976, page 2080, shows an Exclusive OR circuit which performs a logical function of (A.multidot.B.multidot.C.multidot.D) V (E.multidot.F.multidot.G.multidot.H). It shows a circuit structure constructed in accordance with a Schottky diode-transistor logic to perform the above logic function.
None of the prior art teaches a 3-way Exclusive OR logic circuit which includes essentially single stage logic delay, does not require a multi-level current switch tree and hence does not require a high voltage supply, and does not require both true and complement input operands.